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spt7760 8-bit, 1 gsps, flash a/d converter october 2002 features 1:2 demuxed ecl compatible outputs wide input bandwidth ?900 mhz ? ow input capacitance ?15 pf metastable errors reduced to 1 lsb monolithic for low cost ? ra y code output applications digital oscilloscopes ? r ansient capture radar, ew, ecm direct rf down-conversion general description the spt7760 is a full parallel (flash) analog-to-digital con- ve r ter capable of digitizing full scale (0 to ? v) inputs into eight-bit digital words at an update rate of 1 gsps. the ecl-compatible outputs are demultiplexed into two sepa- r ate output banks, each with differential data ready outputs to ease the task of data capture. the spt7760s wide input bandwidth and low capacitance eliminate the need for ex- ternal track-and-hold amplifiers for most applications. a proprietary decoding scheme reduces metastable errors to the 1 lsb level. the spt7760 operates from a single ?.2 v supply, with a nominal power dissipation of 5.5 w. the spt7760 is available in an 80-lead surface-mount mquad package over the industrial temperature range (?5 c to +85 c).

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2 october 2002 spt7760 absolute maximum ratings (beyond which damage may occur) 1 25 c note: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied conditions in typical applications. electrical specifications t j = t c = t a = +25 c , v ee =?.2 v, v rb =?.0 v, v rm =?.0 v, v rt =0.00 v, clk =1 ghz, duty cycle=50%, unless otherwise specified. test test spt7760a spt7760b p arameters conditions level min typ max min typ max units resolution 88 bits dc accuracy integral linearity error (ile) clk = 100 khz i ?.0 +1.0 ?.5 +1.5 lsb differential linearity error (dle) clk = 100 khz i ?.85 +0.95 ?.95 +1.5 lsb no missing codes guaranteed guaranteed analog input input voltage range i v rb v rt v rb v rt v input bias current v in =0 v i .75 2.0 .75 2.0 ma input resistance v 15 15 k ? input capacitance over full input range v 15 15 pf input bandwidth small signal v 900 900 mhz large signal v 500 500 mhz offset error v rt iv ?0 +30 ?0 +30 mv offset error v rb iv ?0 +30 ?0 +30 mv input slew rate v5 5 v/ns clock synchronous input currents v 2 2 a reference input ladder resistance i 60 80 60 80 ? reference bandwidth v 30 30 mhz timing characteristics maximum sample rate i 1 1 ghz aperture jitter v 2 2 ps acquisition time v 250 250 ps clock to data delay iv 0.9 1.4 1.9 0.9 1.4 1.9 ns clk to data ready delay iv 1.25 1.75 2.25 1.25 1.75 2.25 ns dynamic performance signal-to-noise ratio (without harmonics) in = 50 mhz i 45 43 db in = 250 mhz i 43 41 db t otal harmonic distortion in = 50 mhz i 44 42 dbc in = 250 mhz i 36 34 dbc signal-to-noise and distortion in = 50 mhz i 42 40 db in = 250 mhz i 35 33 db supply voltages negative supply voltage (v ee to gnd) ?.0 to +0.5 v ground voltage differential .................... ?.5 to +0.5 v input voltage analog input voltage ............................... +0.5 v to v ee reference input voltage .......................... +0.5 v to v ee digital input voltage ................................ +0.5 v to v ee reference current v rt to v rb ........................... 35 ma output digital output current ............................... 0 to ?8 ma t emperature operating temperature, ambient ............ ?5 to +85 c case .......................... +125 c junction ...................... +150 c lead temperature, (soldering 10 seconds) ...... +300 c storage temperature ............................ ?5 to +150 c
3 october 2002 spt7760 test level codes all electrical characteristics are subject to the fo llowing conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- fo r med during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. unless otherwise noted, all test are pulsed tests; therefore, t j = t c = t a . level test procedure i 100% production tested at the specified temperature. ii 100% production tested at t a = +25 c, and sample tested at the specified temperatures. iii qa sample tested only at the specified temperatures. iv pa r ameter is guaranteed (but not tested) by design and characteri- zation data. vp arameter is a typical value for information purposes only. vi 100% production tested at t a = +25 c. pa r ameter is guaranteed ov er specified temperature range. electrical specifications t j = t c = t a = +25 c , v ee =?.2 v, v rb =?.0 v, v rm =?.0 v, v rt =0.00 v, clk =1 ghz, duty cycle=50%, unless otherwise specified. test test spt7760a spt7760b p arameters conditions level min typ max min typ max units dynamic performance spurious free dynamic range in = 50 mhz i 47 43 db in = 250 mhz i 39 35 db digital inputs input high voltage (clk, clk )i ?.1 ?.7 ?.1 ?.7 v input low voltage (clk, clk )i ?.8 ?.5 ?.8 ?.5 v clock pulse width high (t pwh )i0.50.4 0.5 0.4 ns clock pulse width low (t pwl )i0.50.4 0.5 0.4 ns digital outputs logic 1 voltage i ?.1 ?.9 ?.1 ?.9 v logic 0 voltage i ?.8 ?.5 ?.8 ?.5 v rise time 20% to 80% v 450 450 ps f all time 20% to 80% v 450 450 ps po wer supply requirements v oltage v ee iv ?.95 ?.2 ?.45 ?.95 ?.2 ?.45 v current i ee i 1.05 1.2 1.05 1.2 a po wer dissipation i 5.5 6.25 5.5 6.25 w t ypical thermal impedance: jc = +4 c/w.
4 october 2002 spt7760 general description the spt7760 is one of the fastest monolithic 8-bit parallel flash a/d converters available today. the nominal conver- sion rate is 1 gsps and the analog bandwidth is in e xcess of 900 mhz. a major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators (see b lock diagram). this not only reduces clock transient kick- back to the input and reference ladder due to a low ac beta, but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. the preamplifiers act as buffers and stabi- lize the input capacitance so that it remains constant over different input voltage and frequency ranges and therefore makes the part easier to drive than previous flash convert- ers. the preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to ?rip into or out of the active state. this gain reduces metastable states that can cause errors at the output. the spt7760 has true differential analog and digital data paths from the preamplifiers to the output buffers (current mode logic) for reducing potential missing codes while rejecting common mode noise. signature errors are also reduced by careful layout of the analog circuitry. the output drive capability of the device can provide full ecl swings into 50 ? loads. figure 1 ?spt7760 typical interface circuit
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5 october 2002 spt7760 typical interface circuit the circuit in figure 1 is intended to show the most elabo- r ate method of achieving the least error by correcting for integral linearity, input induced distortion, and power sup- ply/ground noise. this is achieved by the use of external reference ladder tap connections, input buffer, and supply decoupling. please contact the factory for the spt7760 ev aluation board application note that contains more details on interfacing the spt7760. the function of each pin and external connections to other components is as f ollows: v ee , a gnd, dgnd v ee is the supply pin with agnd as ground for the device. the power supply pins should be bypassed as close to the device as possible with at least a .01 f ceramic capaci- tor. a 10 f tantalum can also be used for low frequency suppression. dgnd is the ground for the ecl outputs and is to be referenced to the output pulldown voltage and ap- propriately bypassed as shown in figure 1. v in (analog input) there are two analog input pins that are tied to the same point internally. either one may be used as an analog input sense and the other for input force. this is convenient for testing the source signal to see if there is sufficient drive capability. the pins can also be tied together and driven by the same source. the spt7760 is superior to similar de- vices due to a preamplifier stage before the comparators. this makes the device easier to drive because it has con- stant capacitance and induces less slew rate distortion. clk, clk (clock inputs) the clock inputs are designed to be driven differentially with ecl levels. the duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. if this is not important to the intended application, then duty cycles other than 50% may be used. d0 to d8, dr, dr , (a and b) the digital outputs can drive 50 ? to ecl levels when pulled down to ? v. when pulled down to ?.2 v, the out- puts can drive 130 ? to 1 k ? loads. all digital outputs are gr ey code with the coding as shown in table i. fairchild rec- ommends using differential receivers on the outputs of the data ready lines to ensure the proper output rise and fall times. v rbf , v rbs , v rtf , v rts , v rm (reference inputs) there are two reference inputs and one external reference v oltage tap. these are ? v (v rb f orce and sense), mid- tap (v rm ) and agnd (v rt f orce and sense). the refer- ence pins and tap can be driven by op amps as shown in figure 1 or v rm may be bypassed for limited temperature operation. these voltage inputs can be bypassed to a gnd for further noise suppression if so desired. ta ble i ?output coding v in d8 d7 . . . d8 >?.5 lsb 1 1 0 0 0 0 0 0 0 ?.5 lsb 1 1 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 ?.5 lsb 0 1 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1 ?.0 v 0 1 1 0 0 0 0 0 0 00 1 0 0 0 0 0 0 ?.0 v +0.5 lsb 0 0 0 0 0 0 0 0 1 00 0 0 0 0 0 0 0 <(?.0 v +0.5 lsb) 0 0 0 0 0 0 0 0 0 indicates the transition between the two codes thermal management the typical thermal impedance is as follows: ca = +17 c/w in still air with no heat sink we highly recommend that a heat sink be used for this device with adequate air flow to ensure rated performance of the device. we have found that a thermalloy 17846 heat sink with a minimum air flow of 1 meter/second (200 linear feet per minute) provides adequate thermal perfor- mance under laboratory tests. application specific condi- tions should be taken into account to ensure that the device is properly heat sinked.
6 october 2002 spt7760 operation the spt7760 has 256 preamp/comparator pairs which are each supplied with the voltage from v rt to v rb divided equally by the resistive ladder as shown in the block dia- gr am. this voltage is applied to the positive input of each preamplifier/comparator pair. an analog input voltage ap- plied at v in is connected to the negative inputs of each preamplifier/comparator pair. the comparators are then clocked through each ones individual clock buffer. when the clk pin is in the low state, the master or input stage of the comparators compare the analog input voltage to the respective reference voltage. when the clk pin changes from low to high the comparators are latched to the state prior to the clock transition and output logic codes in se- quence from the top comparators, closest to v rt (0 v), down to the point where the magnitude of the input signal changes sign (thermometer code). the output of each comparator is then registered into four 64-to-6 bit decod- ers when the clk is changed from high to low. at the out- put of the decoders is a set of four 7-bit latches which are enabled (?rack? when the clock changes from high to low. f rom here, the output of the latches are coded into 6 lsbs from 4 columns and 4 columns are coded into 2 msbs. finally, 8 ecl output latches and buffers are used to drive the external loads. the conversion takes one clock cycle from the input to the data outputs. figure 2 ?timing diagram ( #$ #$ %>% (d (, (, ( (, (, (, (, (, (, (d ( (, (, .%< b .%< b %>% .
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7 october 2002 spt7760 figure 3 ?subcircuit schematics input circuit output circuit clock input 5( ( && 5( % 5( 5( #$ && #$ pa ckage outline 80-lead mquad ) e % $ # & f 5 % % inc hes millimeters symbol min max min max a 0.904 0.923 22.95 23.45 b 0.777 0.781 19.74 19.84 c 0.472 typ 12.00 typ d 0.541 0.545 13.74 13.84 e 0.667 0.687 16.95 17.45 f 0.031 typ 0.80 typ g 0.012 0.018 0.30 0.45 h 0.109 0.134 2.76 3.40 i 0.010 0.024 0.25 0.60 j 0.724 typ 18.40 typ k 0.099 0.110 2.51 2.80 l0 7 0 7 m 0.029 0.041 0.73 1.03
8 october 2002 spt7760 ordering information part number description temperature range package SPT7760AIK ile = 1.0 lsb ?5 to +85 c 80l mquad spt7760bik ile = 1.5 lsb ?5 to +85 c 80l mquad pin assignments pin functions name function v ee negative supply nominally ?.2 v a gnd analog ground v rtf reference voltage force top, nominally 0 v v rts reference voltage sense top v rm reference voltage middle, nominally ? v v rbf reference voltage force bottom, nominally ? v v rbs reference voltage sense bottom v in analog input voltage, can be either voltage or sense dgnd digital ground d0?7a data output bank a d0?7b data output bank b dra data ready bank a dra not data ready bank a drb data ready bank b drb not data ready bank b d8a overrange output bank a d8b overrange output bank b clk clock input clk clock input 5( && && 5( 5( (=# (=# 5( 5( 5( 5( && && ) && && /
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g+ && && && && && ( ( && && life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. www.fairchildsemi.com ?copyright 2002 fairchild semiconductor corporation

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